Silicon Labs /Series1 /EFM32GG11B /EFM32GG11B420F2048IM64 /ETH /IMOD

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as IMOD

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RXINTMOD0TXINTMOD

Description

Interrupt moderation register

Fields

RXINTMOD

Count of 800ns periods before bit 1 is set in the interrupt status register after a frame is received

TXINTMOD

Count of 800ns periods before bit 7 is set in the interrupt status register after a frame is transmitted

Links

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